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PRELIMINARY
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
18-Mbit QDRTM-II SRAM 4-Word Burst Architecture
Features
* Separate Independent Read and Write data ports -- Supports concurrent transactions * 250-MHz clock for high bandwidth * 4-Word Burst for reducing address bus frequency * Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) at 250 MHz * Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only * Two output clocks (C and C) account for clock skew and flight time mismatching * Echo clocks (CQ and CQ) simplify data capture in high-speed systems * Single multiplexed address input bus latches address inputs for both Read and Write ports * Separate Port Selects for depth expansion * Synchronous internally self-timed writes * Available in x8, x9, x18, and x36 configurations * Full data coherency providing most current data * Core VDD = 1.8(+/-0.1V); I/O VDDQ = 1.4V to VDD) * 15 x 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 x 15 matrix) * Variable drive HSTL output buffers * JTAG 1149.1 compatible test access port * Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311BV18) or 9-bit words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or 36-bit words (CY7C1315BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds". Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1311BV18-2M x 8 CY7C1911BV18-2M x 9 CY7C1313BV18-1M x 18 CY7C1315BV18-512K x 36
Cypress Semiconductor Corporation Document Number: 38-05620 Rev. **
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised July 23, 2004
PRELIMINARY
Logic Block Diagram (CY7C1311BV18)
D[7:0] 8
Write Write Write Write Reg Reg Reg Reg
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
19
Write Add. Decode
Read Add. Decode
A(18:0)
Address Register
Address Register
19
A(18:0)
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
Read Data Reg. 32 Control Logic 16 Reg. 16 Reg. 8 Reg.
CQ CQ
VREF WPS NWS[1:0]
8
Q[7:0]
Logic Block Diagram (CY7C1911BV18)
D[8:0] 9
Write Write Write Write Reg Reg Reg Reg
19
Write Add. Decode
Read Add. Decode
A(18:0)
Address Register
Address Register
19
A(18:0)
512K x 9 Array
512K x 9 Array
512K x 9 Array
512K x 9 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 9 Reg.
CQ CQ
VREF WPS BWS[0]
9
Q[8:0]
Document Number: 38-05620 Rev. **
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PRELIMINARY
Logic Block Diagram (CY7C1313BV18)
D[17:0] 18
Write Write Write Write Reg Reg Reg Reg
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
18
Write Add. Decode
Read Add. Decode
A(17:0)
Address Register
Address Register
18
A(17:0)
256K x 18 Array
256K x 18 Array
256K x 18 Array
256K x 18 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 18 Reg.
CQ CQ
VREF WPS BWS[1:0]
18
Q[17:0]
Logic Block Diagram (CY7C1315BV18)
D[35:0] 36
Write Write Write Write Reg Reg Reg Reg
17
Write Add. Decode
Read Add. Decode
A(16:0)
Address Register
Address Register
17
A(16:0)
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
VREF WPS BWS[3:0]
Read Data Reg. 144 Control Logic 72 Reg. 72 Reg. 36 Reg.
CQ CQ
36 Q [35:0]
Selection Guide
250 MHz Maximum Operating Frequency Maximum Operating Current 250 TBD 200 MHz 200 TBD 167 MHz 167 TBD Unit MHz mA
Document Number: 38-05620 Rev. **
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PRELIMINARY
Pin Configurations
CY7C1311BV18 (2M x 8)-15 x 17 FBGA
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3
A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11
CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1911BV18 (2M x 9)-15 x 17 FBGA
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK
3
A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/36M NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS
11
CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
Document Number: 38-05620 Rev. **
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PRELIMINARY
Pin Configurations (continued)
CY7C1313V18 (1M x 18)-15 x 17 FBGA
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3
D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/144M NC/36M
CY7C1315AV18 (512K x 36)-15 x 17FBGA
1 A B C D E F G H J K L M N P R
CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO
2
Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3
D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A
10
Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/288M NC/72M
NC/36M NC/144M
Document Number: 38-05620 Rev. **
Page 5 of 23
PRELIMINARY
Pin Definitions
Pin Name D[x:0] I/O Pin Description
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
InputData input signals, sampled on the rising edge of K and K clocks during valid write operaSynchronous tions. CY7C1311BV18 - D[7:0] CY7C1911BV18 - D[8:0] CY7C1313BV18 - D[17:0] CY7C1315BV18 - D[35:0] InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. InputNibble Write Select 0, 1 - active LOW.(CY7C1311BV18 Only) Sampled on the rising edge of Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device.
WPS
NWS0, NWS1,
BWS0, BWS1, InputByte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and K clocks BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1911BV18 - BWS0 controls D[8:0] CY7C1313BV18 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1315BV18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputAddress Inputs. Sampled on the rising edge of the K clock during active Read and Write operaSynchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays each of 512K x 9) for CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1911BV18, 18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18. These inputs are ignored when the appropriate port is deselected. OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1311BV18 - Q[7:0] CY7C1911BV18 - Q[8:0] CY7C1313BV18 - Q[17:0] CY7C1315BV18 - Q[35:0] InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of four sequential transfers. InputClock InputClock InputClock InputClock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. Page 6 of 23
Q[x:0]
RPS
C
C
K
K
Document Number: 38-05620 Rev. **
PRELIMINARY
Pin Definitions (continued)
Pin Name CQ I/O Echo Clock Pin Description
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, "DLL Operation in the QDR-II." TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points. Ground for the device.
CQ
Echo Clock
ZQ
Input
DOFF
Input
TDO TCK TDI TMS NC NC/36M NC/72M
Output Input Input Input N/A N/A N/A N/A N/A InputReference Ground
NC/144M NC/288M
VREF VDD VSS VDDQ
Power Supply Power supply inputs to the core of the device. Power Supply Power supply inputs for the outputs of the device. All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single-clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1313BV18 is described in the following sections. The same basic descriptions apply to CY7C1311BV18, CY7C1911BV18, and CY7C1315BV18. Read Operations The CY7C1313BV18 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data Page 7 of 23
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, CY7C1315BV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to "turn-around" the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1311BV18, four 9-bit data transfers in the case of CY7C1911BV18, four 18-bit data transfers in the case of CY7C1313BV18, and four 36-bit data in the case of CY7C1315BV18 transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C or K and K when in single clock mode).
Document Number: 38-05620 Rev. **
PRELIMINARY
words have been driven out onto Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C or (K or K when in single-clock mode)). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C or K and K when in single-clock mode). When the read port is deselected, the CY7C1313BV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the Write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1313BV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1313BV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, Document Number: 38-05620 Rev. **
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1313BV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location when a Read follows a Write in successive clock cycles, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Depth Expansion The CY7C1313BV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns. Page 8 of 23
PRELIMINARY
Application Example[1]
SRAM #1
Vt R D A R P S # W P S # B W S # R = 250ohms R P S #
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
ZQ CQ/CQ# Q C C# K K#
SRAM #4
D A W P S # B W S #
ZQ R = 250ohms CQ/CQ# Q C C# K K#
DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2
R
Vt Vt
Truth Table[2, 3, 4, 5, 6, 7]
Operation K L-H Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. L-H Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C and C rising edges. NOP: No Operation L-H Standby: Clock Stopped Stopped RPS H[8] WPS L[9] DQ D(A) at K(t+1) DQ D(A + 1) at K(t+1) DQ DQ D(A + 2) at K(t + D(A + 3) at 2) K(t +2)
L[9]
X
Q(A) at C(t +1)
Q(A + 1) at C(t + 2)
Q(A + 2) at C(t Q(A + 3) at C(t + 2) + 3)
H X
H X
D=X D=X D=X D=X Q = High-Z Q = High-Z Q = High-Z Q = High-Z Previous State Previous State Previous State Previous State
[2, 10]
Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18)
BWS0/NWS0 BWS1/NWS1 K L L L-H K -
L
L
-
Comments During the Data portion of a Write sequence: CY7C1311BV18 - both nibbles (D[7:0]) are written into the device, CY7C1313BV18 - both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence: CY7C1311BV18 - both nibbles (D[7:0]) are written into the device, CY7C1313BV18 - both bytes (D[17:0]) are written into the device.
Notes: 1. The above application shows four QDR-II being used. 2. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. "A" represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst. 5. "t" represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the "t" clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read or Write request. 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05620 Rev. **
Page 9 of 23
PRELIMINARY
Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18) (continued)[2, 10]
BWS0/NWS0 BWS1/NWS1 K L H L-H K -
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
L
H
H
L
H
L
H H
H H
Comments During the Data portion of a Write sequence : CY7C1311BV18 - only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313BV18 - only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. - L-H During the Data portion of a Write sequence : CY7C1311BV18 - only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313BV18 - only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L-H - During the Data portion of a Write sequence : CY7C1311BV18 - only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313BV18 - only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. - L-H During the Data portion of a Write sequence : CY7C1311BV18 - only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313BV18 - only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. L-H - No data is written into the devices during this portion of a write operation. - L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions[2, 10](CY7C1315BV18)
BWS0 BWS1 BWS2 BWS3 L L L L L L L H H H H H H H H L H H L L H H H H H H L H H H H L L H H H H L H H H H H H L L H H K L-H - L-H - L-H - L-H - L-H - L-H - L-H - L-H K - L-H - L-H - L-H - L-H Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Write Cycle Descriptions[2, 10] (CY7C1911BV18)
BWS0 L L H H K L-H - L-H - K - L-H - L-H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Page 10 of 23
Document Number: 38-05620 Rev. **
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .... -10C to +85C Supply Voltage on VDD Relative to GND........ -0.5V to +2.9V DC Applied to Outputs in High-Z .........-0.5V to VDDQ + 0.3V DC Input Voltage[14] ............................ -0.5V to VDDQ + 0.3V Current into Outputs (LOW) .........................................20 mA Range Com'l
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Latch-up Current..................................................... >200 mA
Operating Range
Ambient Temperature (TA) 0C to +70C VDD[15] 1.8 0.1V VDDQ[15] 1.4V to VDD
DC Electrical Characteristics Over the Operating Range[11]
Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[14] Input LOW Voltage[14] Input Load Current Output Leakage Current Input Reference Voltage[16] VDD Operating Supply GND VI VDDQ GND VI VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz 250 MHz ISB1 Automatic Power-down Current 167 MHz Max. VDD, Both Ports Deselected, VIN VIH or 200 MHz VIN VIL 250 MHz f = fMAX = 1/tCYC, Inputs Static Note 12 Note 13 IOH = -0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 1.7 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.3 -5 -5 0.68 0.75 Typ. 1.8 1.5 Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF - 0.1 5 5 0.95 TBD TBD TBD TBD TBD TBD Unit V V V V V V V V A A V mA mA mA mA mA mA
Notes: 11. All Voltage referenced to Ground. 12. Output are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 <= RQ <= 350s. 13. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 <= RQ <= 350s. 14. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2). 15. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 38-05620 Rev. **
Page 11 of 23
PRELIMINARY
AC Electrical Characteristics Over the Operating Range
Parameter VIH VIL Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Test Conditions Min. VREF + 0.2 -
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Typ. - -
Max. - VREF - 0.2
Unit V V
Switching Characteristics Over the Operating Range[17, 18]
Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHCH tKHKH tKHKL tKLKH tKHKH tKHCH 250 MHz Description VDD(Typical) to the First Access Input Clock (K/K; C/C) HIGH Input Clock (K/K; C/C) LOW K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) Address Set-up to K Clock Rise Control Set-up to Clock (K, K) Rise (RPS, WPS) Double Data Rate Control Set-up to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Set-up to Clock (K/K) Rise Address Hold after Clock (K/K) Rise Control Hold after Clock (K /K) Rise (RPS, WPS) Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise C/C Clock Rise (or K/K in single clock mode) to Data Valid Data Output Hold after Output C/C Clock Rise (Active to Active) C/C Clock Rise to Echo Clock Valid Echo Clock Hold after C/C Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20] Clock (C and C) Rise to Low-Z[19, 20]
[21]
200 MHz Min. 1 5.0 2.0 2.0 2.2 0.0 - - 2.2 Max. 6.3
167 MHz Min. 1 6.0 2.4 2.4 2.7 0.0 8.4 - - - 2.7 Max. Unit ms ns ns ns ns ns
Min. 1 4.0 1.6 1.6 1.8 0.0
Max. 5.25 - - - 1.8
K Clock and C Clock Cycle Time
Set-up Times tSA tSC tSCDDR tSD Hold Times tHA tHC tHCDDR tHD tCO tDOH tCCQO tCQOH tCQD tCQDOH tCHZ tCLZ tHA tHC tHC tHD tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHZ tCLZ 0.5 0.5 0.35 0.35 - -0.45 - -0.45 - -0.30 - -0.45 - - - - 0.45 - 0.45 - 0.30 - 0.45 - 0.6 0.6 0.4 0.4 - -0.45 - -0.45 - -0.35 - -0.45 - - - - 0.45 - 0.45 - 0.35 - 0.45 - 0.7 0.7 0.5 0.5 - -0.50 - -0.50 - -0.40 - -0.50 - - - - 0.50 - 0.50 - 0.40 - 0.50 - ns ns ns ns ns ns ns ns ns ns ns ns tSA tSC tSC tSD 0.5 0.5 0.35 0.35 - - - - 0.6 0.6 0.4 0.4 - - - - 0.7 0.7 0.5 0.5 - - - - ns ns ns ns
Output Times
Notes: 17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads. 19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 100 mV from steady-state voltage. 20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated.
Document Number: 38-05620 Rev. **
Page 12 of 23
PRELIMINARY
Switching Characteristics Over the Operating Range[17, 18] (continued)
Cypress Consortium Parameter Parameter DLL Timing tKC Var tKC lock tKC Reset tKC Var tKC lock tKC Reset Clock Phase Jitter DLL Lock Time (K, C) K Static to DLL Reset - 1024 30 0.20 - - 1024 30 250 MHz Description Min. Max.
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
200 MHz Min. Max. 0.20 -
167 MHz Min. - 1024 30 Max. 0.20 - Unit ns cycles ns
Thermal Resistance[22]
Parameter JA JC Description Test Conditions 165 FBGA Package TBD TBD Unit C/W C/W
Thermal Resistance Test conditions follow standard test methods and procedures for (Junction to Ambient) measuring thermal impedance, per EIA/JESD51. Thermal Resistance (Junction to Case)
Capacitance[22]
Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. TBD TBD TBD Unit pF pF pF
AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V RQ = 250 (a) 0.75V VREF OUTPUT Device Under ZQ Test 5 pF RQ = 250 (b) 0.25V Slew Rate = 2V / ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[14]
ZQ
Including jig and scope
Note: 22. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05620 Rev. **
Page 13 of 23
PRELIMINARY
Switching Waveforms[23, 24, 25]
Read/Write/Deselect Sequence
NOP 1
K tKH K t KL t CYC tKHKH
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
READ 2
WRITE 3
READ 4
WRITE 5
NOP 6
7
RPS tSC WPS A A0 t SA t HA A1 t HD t SD D D10 D11 A2 A3 t HD t SD D12 D13 D30 D31 D32 D33 tHC tSC tHC
Q
Qx2
Qx3
Q00
Q01 tCO
Q02
Q03
Q20
tDOH
Q21
Q22
Q23
tKHCH t CLZ t CO C tKHCH C tCYC tKHKH
t CHZ tCQD
tDOH
tCQDOH
tKH
t KL
t CCQO t CQOH CQ t CCQO t CQOH CQ
DON'T CARE
UNDEFINED
Notes: 23. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 24. Output are disabled (High-Z) one clock cycle after a NOP. 25. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 38-05620 Rev. **
Page 14 of 23
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port--Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document Number: 38-05620 Rev. **
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 15 of 23
PRELIMINARY
is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the "extest output bus tristate", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
Document Number: 38-05620 Rev. **
Page 16 of 23
PRELIMINARY
TAP Controller State Diagram[26] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1
Note: 26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
1
1 SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
0
Document Number: 38-05620 Rev. **
Page 17 of 23
PRELIMINARY
TAP Controller Block Diagram 0 Bypass Register TDI Selection Circuitry 31 30 29 . . 2 Instruction Register 2 1 0 1 0
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Selection Circuitry
TDO
Identification Register 106 . . . . 2 1 0
Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 14, 27]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDD Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A 0.65VDD -0.3 -5 Min. 1.4 1.6 0.4 0.2 VDD + 0.3 0.35VDD 5 Max. Unit V V V V V V A
TAP AC Switching Characteristics Over the Operating Range [28, 29]
Parameter tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 ns ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 10 10 10 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 40 40 Description Min. 50 20 Max. Unit ns MHz ns ns
Notes: 27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 28. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 29. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05620 Rev. **
Page 18 of 23
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range [28, 29] (continued)
Parameter Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid Description
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Min.
Max. 20
Unit ns ns
0
TAP Timing and Test Conditions[29]
0.9V 1.8V 50 TDO Z0 = 50 CL = 20 pF 0.9V 0V ALL INPUT PULSES
GND
(a)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI Test Data-Out TDO
tTDOV tTDOX
Identification Register Definitions
Value Instruction Field Revision Number (31:29) CY7C1311BV18 000 CY7C1911BV18 000 CY7C1313BV18 000 CY7C1315BV18 000 Description Version number.
Cypress Device ID 11010011011000101 11010011011001101 11010011011010101 11010011011100101 Defines the (28:12) type of SRAM. Cypress JEDEC ID (11:1) ID Register Presence (0) 00000110100 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
1
1
1
1
Document Number: 38-05620 Rev. **
Page 19 of 23
PRELIMINARY
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 107
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z Code 000 001 010 Description Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS
011 100 101 110 111
Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K
Boundary Scan Order (continued)
Bit # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Bump ID 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B
Document Number: 38-05620 Rev. **
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PRELIMINARY
Boundary Scan Order (continued)
Bit # 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Bump ID 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L Bit # 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Boundary Scan Order (continued)
Bump ID 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
Document Number: 38-05620 Rev. **
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PRELIMINARY
Ordering Information
Speed (MHz) 250 Ordering Code CY7C1311BV18-250BZC CY7C1911BV18-250BZC CY7C1313BV18-250BZC CY7C1315BV18-250BZC 200 CY7C1311BV18-200BZC CY7C1911BV18-200BZC CY7C1313BV18-200BZC CY7C1315BV18-200BZC 167 CY7C1311BV18-167BZC CY7C1911BV18-167BZC CY7C1313BV18-167BZC CY7C1315BV18-167BZC BB165E 15 x 17 x 1.4 mm FBGA BB165E 15 x 17x 1.4 mm FBGA Package Name BB165E Package Type 15 x 17 x 1.4 mm FBGA
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Operating Range Commercial
Commercial
Commercial
Package Diagram
165-Ball FBGA (15 x 17 x 1.40 mm) Pkg. Outline (0.50 Ball Dia.) BB165E
BOTTOM VIEW TOP VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.50
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5
PIN 1 CORNER
+0.14 (165X) -0.06
4 3 2 1
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 0.530.05 0.25 C 0.410.05 10.00 0.15 C B 0.15(4X) SEATING PLANE C 0.36 1.40 MAX. 15.000.10
1.00
51-85195-**
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document Number: 38-05620 Rev. ** Page 22 of 23
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
PRELIMINARY
Document History Page
CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18 18-Mbit QDRTM-II SRAM 4-Word Burst Architecture Document Number: 38-05620 REV. ** ECN NO. 252474 ISSUE DATE See ECN ORIG. OF CHANGE DESCRIPTION OF CHANGE SYT New Data Sheet
Document Number: 38-05620 Rev. **
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